设计原理 计数时钟由模为60的秒计数器模块、模为60的分计数模块、模为24的小时计数器模块、指示灯与报警器的模块、分/小时设定模块及输出显示模块等组成。秒计数器模块的进位输出为分计数器模块的进位输入，分计数器模块的进位输出为小时计数器模块的进位输入。其中秒计数器模块中应有分钟的设定，分计数器模块中应有小时的设定。 内容 设计一个计数时钟，使其具有24小时计数功能。通过“多功能复用按键F1-F12”信号接线组“F1_12(T)”的F9~F12的任意引线插孔可设置小时和分钟的值，并具有整点报时的功能。 电路原理图 模块说明：计数时钟由60秒计数器模块XSECOND、60分计数器模块XMINUTE、24小时计数器模块XHOUR等六个模块构成。秒计数器模块的进位输出为分计数器模块的进位输入，分计数器模块中有小时的设定。通过SW1、SW2、SW3、SW4可设定小时和分钟的值，并具有整点报时的功能。 输入信号：SETMIN为分钟设置信号；SETHOUR为小时设置信号；RESET为全局复位信号；CLK为全局时钟信号；CKDSP为数码管动态扫描信号。 输出信号：SPEAK为蜂鸣器报时信号；LAMP[2..0]为指示灯信号；A~G为数码管七个段位信号；SS[2..0]为数码管段位译码控制信号。 说明与电路连线 指示灯信号LAMP2~LAMP0为独立扩展下载板上CPLD器件的第11、10、9脚，内部已连接并已锁定，无需外接连线。 蜂鸣器报时信号SPEAK为独立扩展下载板CPLD器件的第31脚，内部已连接并已锁定，无需外接连线。 拨码开关SW1~SW7内部已连接并已锁定，无需外接连线。 数码管七个段位信号A~G为独立扩展下载板上CPLD器件的第86、87、88、89、90、92、93脚，应接数码管段位引线接线组KPL_AH，从左到右依次对应的A、B、C、D、E、F、G引线插孔。 数码管段位译码控制信号SS0、SS1、SS2为独立扩展下载板上CPLD器件的第68、69、70脚，为数码管的位选扫描信号，分别接信号接线组DS1-8A（T）的SS0、SS1、SS2引线插孔（即在电源引线插孔组GND孔处）。 复位信号RESET为独立扩展下载板上CPLD器件的第71脚，应接“多功能复用按键F1-F12”信号接线组“F1_12(T)”的F9~F12的任意一个插孔。 小时设置信号SETHOUR为独立扩展下载板CPLD器件的第73脚，应接“多功能复用按键F1-F12”信号接线组“F1_12(T)”的F9~F12的任意一个插孔。 分钟设置信号SETMIN为独立扩展下载板上CPLD器件的第74脚，应接“多功能复用按键F1-F12”信号接线组“F1_12(T)”的F9~F12的任意一个插孔。 时钟信号CLK为独立扩展下载板上CPLD器件的183脚（即GCLK2），应接时钟信号接线组“CLOCK（T）”的“FRQ（21）”引线插孔。 数码管动态扫描信号CKDSP为独立扩展下载板上CPLD器件的79脚（即GCLK1），应接时钟信号接线组“CLOCK（T）”的“FRQ（11）”引线插孔。 参考源程序 library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xsecond is port ( clk: in STD_LOGIC; clkset: in STD_LOGIC; setmin: in STD_LOGIC; reset: in STD_LOGIC; secout: out STD_LOGIC_VECTOR (6 downto 0); enmin: out STD_LOGIC ); end xsecond; architecture xsecond_arch of xsecond is signal sec : std_logic_vector(6 downto 0); signal emin : std_logic; signal sec1 : std_logic; begin -- <> process(reset,sec,emin,setmin,clkset) begin if reset='0' then enmin<='0'; secout<=0000000; sec1<='1'; else sec1<='0'; secout<=sec; if clkset='1' and clkset'event then if setmin='0' then enmin<='1'; else enmin<=emin; end if; end if; end if; end process; process(clk,sec1) alias lcount : std_logic_vector(3 downto 0) is sec(3 downto 0); alias hcount : std_logic_vector(2 downto 0) is sec(6 downto 4); begin if sec1='1' then sec<=0000000; else if (clk='1' and clk'event) then if lcount=9 then lcount<=0000; if hcount/=5 then hcount<=hcount+1; emin<='0'; else hcount<=000; emin<='1'; end if; else lcount<=lcount+1; emin<='0'; end if; end if; end if; end process; end xsecond_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xminute is port ( clkmin: in STD_LOGIC; reset: in STD_LOGIC; sethour: in STD_LOGIC; clk: in STD_LOGIC; minout: out STD_LOGIC_VECTOR (6 downto 0); enhour: out STD_LOGIC ); end xminute; architecture xminute_arch of xminute is signal min : std_logic_vector(6 downto 0); signal ehour : std_logic; signal min1 : std_logic; begin -- <> process(reset,clk,sethour,min,ehour) begin if reset='0' then enhour<='0'; minout<=0000000; min1<='0'; else min1<='1'; minout<=min; if clk='1' and clk'event then if sethour='0' then enhour<='1'; else enhour<=ehour; end if; end if; end if; end process; process(clkmin,min1) alias lcountm : std_logic_vector(3 downto 0) is min(3 downto 0); alias hcountm : std_logic_vector(2 downto 0) is min(6 downto 4); begin if min1='0' then min<=0000000; else if (clkmin='1' and clkmin'event) then if lcountm=9 then lcountm<=0000; if hcountm/=5 then hcountm<=hcountm+1; ehour<='0'; else hcountm<=000; ehour<='1'; end if; else lcountm<=lcountm+1; ehour<='0'; end if; end if; end if; end process; end xminute_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xhour is port ( clkhour: in STD_LOGIC; reset: in STD_LOGIC; hourout: out STD_LOGIC_VECTOR (5 downto 0) ); end xhour; architecture xhour_arch of xhour is signal hour : std_logic_vector(5 downto 0); begin -- <> process(reset,clkhour,hour) alias lcount : std_logic_vector(3 downto 0) is hour(3 downto 0); alias hcount : std_logic_vector(1 downto 0) is hour(5 downto 4); begin if reset='0' then hourout<=000000; hour<=000000; else if (clkhour='1' and clkhour'event) then if lcount=9 then lcount<=0000; hcount<=hcount+1; else if hour=100011 then hour<=000000; else lcount<=lcount+1; end if; end if; end if; hourout<=hour; end if; end process; end xhour_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xalert is port ( clk: in STD_LOGIC; d_in: in STD_LOGIC_VECTOR (6 downto 0); speak: out STD_LOGIC; d_out: out STD_LOGIC_VECTOR (2 downto 0) ); end xalert; architecture xalert_arch of xalert is type state is (s1,s2,s3,s4); signal next_state,current_state : state; begin -- <> process(clk,current_state,d_in) begin if d_in/=0000000 then speak<='0'; next_state<=s1; current_state<=s1; d_out<=000; else if clk='1' and clk'event then speak<='1'; current_state<=next_state; end if; case current_state is when s1 => d_out<=000; next_state<=s2; when s2 => d_out<=001; next_state<=s3; when s3 => d_out<=010; next_state<=s4; when s4 => d_out<=100; next_state<=s1; when others => d_out<=000; null; end case; end if; end process; end xalert_arch; library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xsettime is port ( hour: in STD_LOGIC_VECTOR (5 downto 0); min: in STD_LOGIC_VECTOR (6 downto 0); sec: in STD_LOGIC_VECTOR (6 downto 0); reset: in STD_LOGIC; clk: in STD_LOGIC; sel: out STD_LOGIC_VECTOR (2 downto 0); d_out: out STD_LOGIC_VECTOR (3 downto 0) ); end xsettime; architecture xsettime_arch of xsettime is signal sel1 : std_logic_vector(2 downto 0); begin -- <> process(clk,reset,sel1,hour,min,sec) begin if reset='0' then sel<=000; d_out<=0000; sel1<=000; else if (clk='1' and clk'event) then if sel1<5 then sel1<=sel1+1; else sel1<=000; end if; end if; sel<=sel1; case sel1 is when 000 => d_out(3)<='0'; d_out(2)<='0'; d_out(1)<=hour(5); d_out(0)<=hour(4); when 001 => d_out<=hour(3 downto 0); when 010 => d_out(3)<='0'; d_out(2)<=min(6); d_out(1)<=min(5); d_out(0)<=min(4); when 011 => d_out<=min(3 downto 0); when 100 => d_out(3)<='0'; d_out(2)<=sec(6); d_out(1)<=sec(5); d_out(0)<=sec(4); when 101 => d_out<=sec(3 downto 0); when others => null; end case; end if; end process; end xsettime_arch; library IEEE; use IEEE.std_logic_1164.all; entity xdeled is port ( d_in: in STD_LOGIC_VECTOR (3 downto 0); a: out STD_LOGIC; b: out STD_LOGIC; c: out STD_LOGIC; d: out STD_LOGIC; e: out STD_LOGIC; f: out STD_LOGIC; g: out STD_LOGIC ); end xdeled; 才五分啊，太少了吧